1. Field of the Invention
The present invention relates to a level conversion circuit.
2. Description of the Related Art
In recent years, a semiconductor device is configured of a plurality of logic circuits to carry out complicated processing appropriately. The logic circuits in the semiconductor device include a TTL (Transistor Transistor Logic) circuit and a CMOS logic circuit or the like. Connection of the logic circuits is provided through interfaces inside the semiconductor device, and the interfaces such as a TTL interface and a CMOS interface corresponding to the logic circuits are employed as the interfaces in the semiconductor device.
An operation speed of the semiconductor circuit has increased in conjunction with the development of a semiconductor technology. A data transfer rate has been accelerated to an order of Gbps in the past few years. A higher data transfer rate technique between devices is demanded to cope with the accelerated operation speed of the semiconductor device. Since the above conventional interfaces such as the TTL interface and the CMOS interface require a relatively large amplitude level, data transfer cannot be carried out at an appropriate rate in case of the frequency of a bus clock signal of 100 MHz or more. Therefore, a differential interface such as LVDS (Low Voltage Differential Signaling) is essential to the above Gbps order data transfer. In a data communication using the differential data transfer, a conversion circuit is provided between the TTL circuit and the CMOS logic circuit which are provided for blocks, and a differential data transfer circuit is provided in another block. Integration of these circuits in one chip is available due to the progress of semiconductor technology in recent years. Thus, various merits are realized such as low-cost manufacture of a high-speed data transfer device and reduction of a substrate chip area. Accordingly, the above usual logic circuit and the differential data transfer circuit are often mixed in the semiconductor device.
The usual logic circuit employs a one-wire system (hereinafter, to be referred to as a single end interface) to transfer a signal by using a single line except for a ground. On the other hand, the differential transmission circuit such as a CML (Current Mode Logic) used for a signal data transfer of an Ethernet (registered trademark), and a PECL/LVPECL that is widely used in a high-speed clock supply circuit, employs a two-wire system to transfer a signal by using two lines (hereinafter, to be referred to as a differential interface).
The single end interface to transfer a signal by using one line requires a ground line in addition to a signal line necessarily. In the usual logic circuit, a transferred signal is determined to be an H level if the transferred signal is higher than a predetermined voltage, and to be an L level if the transferred signal is lower than the predetermined voltage. The predetermined voltage is called a threshold voltage. The TTL or CMOS uses a ground potential level as a voltage reference. In the single end interface, the signal level is determined to be as the H level or the L level, by using a potential difference between the ground level and the signal line.
On the other hand, the differential interface requires two signal lines to transfer one signal. The logic “1” or “0” is determined based on whether the potential difference between the two signal lines is positive or negative. Therefore, in the differential interface can transfer a signal even if an amplitude level of the transferred signal is small. Since the differential interface can transfer a signal of the small amplitude, it is suitable to transfer the signal at high speed.
When a signal transferred from the differential interface is converted into a level suitable for the single end interface, in other words, when a logic level of the transferred signal is converted into a different logic level, a duty ratio of the logic level is sometimes deteriorated or changed after the conversion. As a technique to suppress the deterioration of the duty ratio, a technique in which a phase adjustment circuit is provided in the post stage of a level conversion circuit is known as described in Japanese Laid Open Patent Publication (JP-P2000-305528A).
FIG. 1 shows a configuration of a conventional technique according to Japanese Laid Open Patent Publication (JP-P2000-305528A). A conventional level conversion circuit includes two level shifters (LVL) 101 and 103, two inverters 102 and 104 and a phase adjustment circuit 105. The two level shifters (LVL) 101 and 103 convert two-phase clock signals CK and CKX having opposite phases of 5V into two-phase clock signals in the same cycle of 15V. The two inverters 102 and 104 invert the phases of output clock signals from the two level shifters 101 and 103. The phase adjustment circuit 105 adjusts the output clock phases of the two inverters 102 and 104. In the level conversion circuit having the above configuration, the two-phase clock signals CK and CKX having the mutually opposite phases are supplied to input terminals a and b of the level shifter 101, and to input terminals b and a of the level shifter 103. In other words, the level shifters 101 and 103 receive the two-phase clock signals CK and CKX in the opposite phases. The level shifters 101 and 103 have circuit configurations that are practically equivalent to each other, and output single-phase clock signals in the opposite phases. In FIG. 1, the phase adjustment circuit 105 includes a latch circuit 106, in which inverters 107 and 109 invert output clock phases from the inverters 102 and 104, inverters 111 and 112 connected in parallel in the mutually opposite directions to latch respective output clocks of the inverters 107 and 109, and inverters 108 and 110 invert two output clock phases of the latch circuit 106 to output two-phase clocks CK and CKX in the mutually opposite phases.
In the above conventional technique, a positive phase differential signal is supplied to one of the two level shifters and an opposite phase differential signal is supplied to the other level shifter. Accordingly, the two level shifters are required. The inverters are provided between the phase adjustment circuit and the level shifters to avoid the effect of the phase adjustment circuit to the level shifters. The phase adjustment circuit includes two inverters for phase adjustment. Thus, the conventional technique requires at least four inverters.
The phase adjustment circuit generates a desired signal by interpolate output phases of the inverters provided in the post stage of the level shifters. However, it is difficult to apply the technique disclosed in Japanese Laid Open Patent Publication (JP-P2000-305528A) to conversion of the logic level in small amplitude such as the CML level to the CMOS level as demanded in a semiconductor device. Also, an appropriate level conversion circuit in a small circuit scale is demanded for a logic level conversion of a small amplitude signal to a different logic level.